The formation of high quality interconnects is a critical part of ultra large-scale integration (ULSI) integrated circuits. In conventional fabrication processes, vias and upper wiring structures are formed in a dual damascene process. In this type of process, via openings and trenches are formed in a dielectric layer prior to the deposition of metal materials.
In dual damascene processes, though, the via openings have a tapered edge with a smaller cross sectional area (width) at the bottom of the opening than at a top of the opening. Due to this dimensional configuration, via resistance and manufacturability has been degrading at advanced nodes. For example, due to scaling, via resistance has been increasing by greater than 2× the rate of wires. Also, etching and filling of the via openings are becoming increasingly difficult in these advanced nodes. For example, it is becoming ever more difficult to place liners within the via openings without completely filling the via openings with highly resistive material. Also, it becomes very difficult to align the via openings with an underlying metal wiring layer.